The present invention relates generally to semiconductor devices, and more particularly, to the creation of fine granularity etch resistant (hard) masks for efficient sub-micron semiconductor devices fabrication.
As semiconductor devices develop into the sub-micron region and are more highly integrated, interconnections and isolation widths required in the manufacturing processes have become very fine. In general, a fine pattern is formed through a process including forming a resist pattern by a photolithographic technique, and etching various underlying thin films through the resist pattern. The photolithographic technique includes resist coating, mask alignment, exposure to light, and development. This technique has a limit due to the natural limitation of the wavelength of the exposing light. In other words, when using the conventional photolithographic technique, it is difficult to form a critical dimension of a fine resist pattern that exceeds the limit of the wavelength of the exposing light.
Furthermore, the conventional lithographic technique has difficulty in controlling the etching resistance of a resist pattern, making it impossible to fully control a surface profile. As such, the etched pattern on a substrate is relatively rough, especially on the surfaces of the side walls of the etched patterns. As semiconductor fabrication processes delve into the sub-micron level, it is increasingly difficult to obtain fine granularity dimensions with the photolithography technique. In addition, the resist pattern formed by conventional methods is further affected by the use of SEM E beam testing. The SEM E beam test is used for verification of the semiconductor dimensions, but causes shrinkage of the critical dimensions.
Desirable in the art of sub-micron semiconductor device fabrication are new fabrication methods that effectively create fine granularity semiconductor dimensions and provide additional control of the etch resistance to the resist pattern layer.